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| WM8193 16-bit 6msps cis/ccd analogue front end/digitiser wolfson microelectronics ltd w :: www.wolfsonmicro.com advanced information september 2002, rev 2.0 copyright ? 2002 wolfson microelectronics ltd. description the WM8193 is a 16-bit analogue front end/digitiser ic which processes and digitises the analogue output signals from ccd sensors or contact image sensors (cis) at pixel sampleratesofupto6msps. the device includes three analogue signal processing channels each of which contains reset level clamping, correlated double sampling and programmable gain and offset adjust functions. three multiplexers allow single channel processing. the output from each of these channels is time multiplexed into a single high-speed 16-bit analogue-to-digital converter. the digital output data is available in 16-bit parallel or 8 or 4-bit wide multiplexed format, with no missing codes. an internal 4-bit dac is supplied for internal reference level generation. this may be used during cds to reference cis signals or during reset level clamping to clamp ccd signals. alternatively an external reference level may be applied. adc references are generated internally, ensuring optimum performance from the device. using an analogue supply voltage of 5v and a digital interface supply of either 5v or 3.3v, the WM8193 typically only consumes 200mw when operating from a single 5v supply and less than 20 a when in power down mode. features ? 16-bit adc ? 6msps conversion rate ? low power C 192mw typical ? 5v single supply or 5v/3.3v dual supply operation ? single or 3 channel operation ? correlated double sampling ? programmable gain (8-bit resolution) ? programmable offset adjust (8-bit resolution) ? programmable clamp voltage ? 16-bit parallel or 8 or 4-bit wide multiplexed data output formats ? internally generated voltage references ? 48-pin tqfp package ? serial or parallel control interface applications ? flatbed and sheetfeed scanners ? usb compatible scanners ? multi-function peripherals ? high-performance ccd sensor interface block diagram m u x rinp data i/o port sen/stb v smp mclk vrlc/vbias sdi/dna sck/rnw timing control cl rlc/acyc rlc v s r s binp ginp v rx v rt vref/ bias oeb m u x v rb rlc rlc cds cds cds r g b r g b + 8 8 pga 8 8 pga 8 8 4 + + + configurable serial parallel control interface 16- bit adc avdd1-2 op[0] op[1] op[2] op[3] op[4] op[5] op[6] op[7] + + w dvdd1-3 op[8] op[9] op[10] op[11] op[12] op[13] nreset dgnd1-5 agnd1-6 op[14] op[15]/sdo i/p signal polarity adjust i/p signal polarity adjust i/p signal polarity adjust pga offset dac offset dac offset dac m u x m u x rlc dac WM8193
WM8193 advanced information w ai rev 2.0 september 2002 2 pin configuration ordering information device temp. range package xWM8193cft 0 to 70 c 48-pin tqfp 1mm thick body vrt avdd1 avdd2 agnd5 agnd6 vrb op[13] op[14] op[15]/sdo dgnd5 nc nreset 37 47 46 45 44 43 42 41 40 39 38 48 dvdd2 dgnd1 op[3] op[0] op[1] op[2] op[4] vsmp sdi/dna sck/rnw rlc/acyc mclk vrx agnd3 ginp agnd2 binp agnd1 vrlc/vbias rinp agnd4 dvdd1 oeb sen/stb dgnd4 dgnd3 op[9] op[10] op[11] op[12] dvdd3 dgnd2 op[5] op[6] op[7] op[8] 25 31 30 29 28 27 26 36 35 34 33 32 1 9 8 7 6 5 4 3 2 12 11 10 24 23 16 17 18 19 20 21 22 13 14 15 pin description pin name type description 1 vrx analogue output input return bias voltage. this pin must be decoupled to agnd via a capacitor. 2 vrlc/vbias analogue i/o selectable analogue output voltage for rlc or single-ended bias reference. this pin would typically be decoupled to agnd via a capacitor. vrlc can be externally driven if programmed hi-z. 3 agnd1 supply analogue ground (0v). 4 binp analogue input blue channel input video. 5 agnd2 supply analogue ground (0v). 6 ginp analogue input green channel input video. 7 agnd3 supply analogue ground (0v). 8 rinp analogue input red channel input video. 9 agnd4 supply analogue ground (0v). 10 dvdd1 supply digital supply (5v) for logic and clock generator. this must be operated at the same potential as avdd. 11 oeb digital input output hi-z control, all digital outputs disabled when oeb = 1. serial interface: enable pulse, active high parallel interface: strobe, active low 12 sen/stb digital input latched on nreset rising edge: if low then device control is via serial interface, if high then device control is via parallel interface. 13 sdi/dna digital input serial interface: serial input data signal parallel interface: high = data, low = address 14 sck/rnw digital input serial interface: serial clock signal parallel interface: high: op[15:8] is output bus. low: op[15:8] is input bus (hi-z). 15 vsmp digital input video sample synchronisation pulse. 16 rlc/acyc digital input rlc (active high) selects reset level clamp on a pixel-by-pixel basis C tie high if used on every pixel. acyc autocycles between r, g, b inputs when in line-by-line mode. 17 mclk digital input master clock. this clock is applied at n times the input pixel rate (n = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). 18 dgnd1 supply digital ground (0v). advanced information WM8193 w ai rev 2.0 september 2002 3 pin name type description 19 op[0] 20 op[1] 21 op[2] digital output 22 op[3] digital output 23 op[4] digital output pins op[15:0] form a hi-z digital bi-directional bus. there are several modes: hi-z: when oeb = 1. 16-bit output: 16-bit data is output on op[15:0]. 8-bit multiplexed output: data is output on op[15:8] at 2 ? adc conversion rate. 4-bit multiplexed output: data is output on op[15:12] at 4 ? adc conversion rate. see output formats section in device description for further details. input 8-bit: control data is input on op[15:8] in parallel mode when sck/rnw = 0, and sen/stb = 0. output 8-bit: register read back data is output in parallel on op[15:8] when sck/rnw = 1, and sen/stb = 0, or in serial on pin sdo when sen/stb = 1. 24 dvdd2 supply digital i/o supply (3.3v/5v). 25 dgnd2 supply digital ground (0v). 26 op[5] digital output 27 op[6] digital output 28 op[7] digital output 29 op[8] digital i/o see pins 21 to 23 for details. 30 dgnd3 supply digital ground (0v). 31 op[9] digital i/o 32 op[10] digital i/o 33 op[11] digital i/o 34 op[12] digital i/o see pins 21 to 23 for details. 35 dvdd3 supply digital i/o supply (3.3v/5v). 36 dgnd4 supply digital ground (0v). 37 op[13] digital i/o 38 op[14] digital i/o 39 op[15]/sdo digital i/o see pins 21 to 23 for details. if the device has been configured to use the serial interface, pin op[15]/sdo may be used to output register read-back data when oeb = 0 and sen has been pulsed high. see serial interface sections in device description for further details. 40 dgnd5 supply digital ground (0v). 41 nc no connection. 42 nreset digital input reset input, active low. this signal forces a reset of all internal registers and selects whether the serial or parallel control interface is used. see pin sen/stb. 43 avdd1 supply analogue supply (5v). 44 avdd2 supply analogue supply (5v). 45 agnd5 supply analogue ground (0v). 46 agnd6 supply analogue ground (0v). 47 vrb analogue output lower reference voltage. this pin must be capacitively decoupled to agnd. 48 vrt analogue output lower reference voltage. this pin must be capacitively decoupled to agnd. WM8193 advanced information w ai rev 2.0 september 2002 4 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. condition min max analogue supply voltages: avdd1, 2 gnd - 0.3v gnd+7v digital supply voltages: dvdd1 ? 3 gnd - 0.3v gnd+7v digital grounds: dgnd1 ? 5 gnd - 0.3v gnd + 0.3v analogue grounds: agnd1 ? 6 gnd - 0.3v gnd + 0.3v digital inputs, digital outputs and digital i/o pins gnd - 0.3v dvdd2 + 0.3v analogue inputs (rinp, ginp, binp) gnd - 0.3v avdd + 0.3v other pins gnd - 0.3v avdd + 0.3v operating temperature range: t a 0 c +70 c storage temperature -65 c +150 c package body temperature (soldering, 10 seconds) +240 c package body temperature (soldering, 2 minutes) +183 c notes: 1. gnd denotes the voltage of any ground pin. 2. agnd1 ? 6 and dgnd1 ? 5 pins are intended to be operated at the same potential. differential voltages between these pins will degrade performance. recommended operating conditions condition symbolmin typ max units operating temperature range t a 070 c analogue supply voltage avdd1, 2 4.75 5.0 5.25 v digital core supply voltage dvdd1 4.75 5.0 5.25 v 5v i/o dvdd2, 3 4.75 5.0 5.25 v digital i/o supply voltage 3.3v i/o dvdd2, 3 2.97 3.3 3.63 v advanced information WM8193 w ai rev 2.0 september 2002 5 electrical characteristics test conditions avdd1 = avdd2 = dvdd1 = 4.75 to 5.25v, dvdd2 = dvdd3 = 2.97 to 3.63v, agnd = dgnd = 0v, t a =0to70 c, mclk = 12mhz unless otherwise stated. parameter symboltest conditions min typ max unit overall system specification (including 16-bit adc, pga, offset and cds functions) conversion rate 6 msps full-scale input voltage range (see note 1) max gain min gain 0.4 4.08 vp-p vp-p input signal limits (see note 2) v in 0avddv full-scale transition error gain = 0db; pga[7:0] = 4b(hex) 20 mv zero-scale transition error gain = 0db; pga[7:0] = 4b(hex) 20 mv differential non-linearity dnl 1.25 lsb integral non-linearity inl 20 lsb channel to channel gain matching 1% total output noise min gain max gain 3.9 11 lsb rms lsb rms references upper reference voltage vrt 2.85 v lower reference voltage vrb 1.35 v input return bias voltage vrx 1.65 v diff. reference voltage (vrt-vrb) v rtb 1.4 1.5 1.6 v output resistance vrt, vrb, vrx 1 ? vrlc/reset-level clamp (rlc) rlc switching impedance 50 ? vrlc short-circuit current 5ma vrlc output resistance 2 ? vrlc hi-z leakage current vrlc = 0 to avdd 1 a rlcdac resolution 4bits rlcdac step size, rlcdac = 0 v rlcstep avdd=5v 0.25 v/step rlcdac step size, rlcdac = 1 v rlcstep 0.17 v/step rlcdac output voltage at code 0(hex), rlcdacrng = 0 v rlcbot avdd=5v 0.39 v rlcdac output voltage at code 0(hex), rlcdacrng = 1 v rlcbot 0.26 v rlcdac output voltage at code f(hex) rlcdacrng, = 0 v rlctop avdd=5v 4.16 v rlcdac output voltage at code f(hex), rlcdacrng = 1 v rlctop 2.81 v vrlc deviation -50 +50 mv offset dac, monotonicity guaranteed resolution 8bits differential non-linearity dnl 0.1 0.5 lsb integral non-linearity inl 0.25 1 lsb step size 2.04 mv/step output voltage code 00(hex) code ff(hex) -260 +260 mv mv notes: 1. full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. 2. input signal limits are the limits within which the full-scale input voltage signal must lie. WM8193 advanced information w ai rev 2.0 september 2002 6 test conditions avdd1 = avdd2 = dvdd1 = 4.75 to 5.25v, dvdd2 = dvdd3 = 2.97 to 3.63v, agnd = dgnd = 0v, t a =0to70 c, mclk = 12mhz unless otherwise stated. parameter symboltest conditions min typ max unit programmable gain amplifier resolution 8bits gain ] 0 : 7 [ pga 283 208 ? v/v max gain, each channel g max 7.4 v/v min gain, each channel g min 0.74 v/v gain error, each channel 1% analogue to digital converter resolution 16 bits speed 6 msps full-scale input range (2*(vrt-vrb)) 3v digitalspecifications digital inputs high level input voltage v ih 0.8 ? dvdd2/3 v low level input voltage v il 0.2 ? dvdd2/3 v high level input current i ih 1 a low level input current i il 1 a input capacitance c i 5pf digital outputs high level output voltage v oh i oh = 1ma dvdd2/3 - 0.5 v low level output voltage v ol i ol =1ma 0.5 v high impedance output current i oz 1 a digital io pins applied high level input voltage v ih 0.8 ? dvdd2/3 v applied low level input voltage v il 0.2 ? dvdd2/3 v high level output voltage v oh i oh = 1ma dvdd2/3 - 0.5 v low level output voltage v ol i ol =1ma 0.5 v low level input current i il 1 a high level input current i ih 1 a input capacitance c i 5pf high impedance output current i oz 1 a supply currents total supply current ? active (three channel mode) mclk = 12mhz 39 ma total supply current ? active (single channel mode) linebyline = 1 mclk = 12mhz 34 55 ma total analogue supply current ? active (three channel mode) i avdd mclk = 12mhz 35 ma total analogue supply current ? active (one channel mode) i avdd linebyline = 1 mclk = 12mhz 30 ma digital core supply current, dvdd1 ? active (note1) mclk = 12mhz 2ma digital i/o supply current, dvdd2 ? active (note1) mclk = 12mhz 2ma supply current ? full power down mode 20 60 a advanced information WM8193 w ai rev 2.0 september 2002 7 input video sampling mclk vsmp input video t per t mclkh t mclkl t vsmpsu t vsmph t vsu t vh t rsu t rh figure 1 input video timing test conditions avdd1 = avdd2 = dvdd1 = 4.75 to 5.25v, dvdd2 = dvdd3 = 2.97 to 3.63v, agnd = dgnd = 0v, t a =0to70 c, mclk = 12mhz unless otherwise stated. parameter symboltest conditions min typ max units mclk period t per 83.3 ns mclk high period t mclkh 37.5 ns mclk low period t mclkl 37.5 ns vsmp set-up time t vsmpsu 10 ns vsmp hold time t vsmph 5ns video level set-up time t vsu 15 ns video level hold time t vh 5ns reset level set-up time t rsu 15 ns reset level hold time t rh 5ns notes: 1. t vsu and t rsu denote the set-up time required after the input video signal has settled. 2. parameters are measured at 50% of the rising/falling edge. output data timing mclk op[13:0] t pd figure 2 output data timing WM8193 advanced information w ai rev 2.0 september 2002 8 oeb op[15:0] t pze hi-z t pez hi-z figure 3 output data enable timing test conditions avdd1 = avdd2 = dvdd1 = 4.75 to 5.25v, dvdd2 = dvdd3 = 2.97 to 3.63v, agnd = dgnd = 0v, t a =0to70 c, mclk = 12mhz unless otherwise stated. parameter symboltest conditions min typ max units output propagation delay t pd i oh =1ma,i ol =1ma 75 ns output enable time t pze 50 ns output disable time t pez 25 ns mclk rlc/acyc pga/offset mux output t acycsu t acych t acycsu t acych figure 4 auto cycle timing test conditions avdd = dvdd1 = 4.75 to 5.25v, dvdd2 = 2.97 to 3.63v, agnd = dgnd = 0v, t a =0to70 c, mclk = 32mhz unless otherwise stated. parameter symboltest conditions min typ max units auto cycle set-up time t acycsu 10 ns auto cycle hold time t acych 5 ns advanced information WM8193 w ai rev 2.0 september 2002 9 serialinterface figure 5 serial interface timing test conditions avdd1 = avdd2 = dvdd1 = 4.75 to 5.25v, dvdd2 = dvdd3 = 2.97 to 3.63v, agnd = dgnd = 0v, t a =0to70 c, mclk = 12mhz unless otherwise stated. parameter symboltest conditions min typ max units sck period t sper 41.6 ns sck high t sckh 18.8 ns sck low t sckl 18.8 ns sdi set-up time t ssu 6ns sdi hold time t sh 6ns sck to sen set-up time t sce 12 ns sen to sck set-up time t sec 12 ns sen pulse width t sew 25 ns sen low to sdo = register data t serd 30 ns sck low to sdo = register data t scrd 30 ns sck low to sdo = adc data t scadc 30 ns note: parameters are measured at 50% of the rising/falling edge. sck sdi sen sdo t sper t sckl t sckh t ssu t sh t sce t sew t sec t serd t scrd msb lsb t scrdz adc data adc data register data WM8193 advanced information w ai rev 2.0 september 2002 10 parallel interface stb op[15:8] dna rnw adc data out adc data out reg. data out adc data out hi-z hi-z t asu t stb t ah t dsu t dh t stdo t stao t adls t adlh t adhs t adhh t opd address in data in t opz figure 6 parallel interface timing test conditions avdd1 = avdd2 = dvdd1 = 4.75 to 5.25v, dvdd2 = dvdd3 = 2.97 to 3.63v, agnd = dgnd = 0v, t a =0to70 c, mclk = 12mhz unless otherwise stated. parameter symboltest conditions min typ max units rnw low to op[15:8] hi-z t opz 10 ns address set-up time to stb low t asu 0ns dnalowset-uptimetostblow t adls 5ns strobe low time t stb 30 ns address hold time from stb high t ah 5ns dna low hold time from stb high t adlh 5ns data set-up time to stb low t dsu 0ns dna high set-up time to stb low t adhs 5ns data hold time from stb high t dh 5ns data high hold time from stb high t adhh 5ns rnw high to op[15:8] output t opd 30 ns data output propogation delay from stb low t stdo 30 ns adc data out propogation delay from stb high t stao 30 ns note: parameters are measured at 50% of the rising/falling edge. advanced information WM8193 w ai rev 2.0 september 2002 11 device description introduction a block diagram of the device showing the signal path is presented on page 1. the WM8193 samples up to three inputs (rinp, ginp and binp) simultaneously. the device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. each processing channel consists of an input sampling block with optional reset level clamping (rlc) and correlated double sampling (cds), a 8-bit programmable offset dac and an 8-bit programmable gain amplifier (pga). the adc then converts each resulting analogue signal to a 16-bit digital word. the digital output from the adc is presented on a 16-bit wide bus, with optional 8+8-bit or 4+4+4+4-bit multiplexed formats. on-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. these registers are programmable via a serial or parallel interface. input sampling the WM8193 can sample and process one to three inputs through one or three processing channels as follows: colour pixel-by-pixel: the three inputs (rinp, ginp and binp) are simultaneously sampled for each pixel and a separate channel processes each input. the signals are then multiplexed into the adc, which converts all three inputs within the pixel period. monochrome: a single chosen input (rinp, ginp, or binp) is sampled, processed by the corresponding channel, and converted by the adc. the choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. colour line-by-line: a single chosen input (rinp, ginp, or binp) is sampled and multiplexed into the red channel for processing before being converted by the adc. the input selected can be switched in turn (rinp ginp binp rinp) together with the pga and offset dac control registers by pulsing the rlc/acyc pin. this is known as auto-cycling. alternatively, other sampling sequences can be generated via the control registers. this mode causes the blue and green channels to be powered down. refer to the line-by-line operation section for more details. reset level clamping (rlc) to ensure that the signal applied to the WM8193 lies within its input range (0v to avdd) the ccd output signal is usually level shifted by coupling through a capacitor, c in. the rlc circuit clamps the WM8193 side of this capacitor to a suitable voltage during the ccd reset period. a typical input configuration is shown in figure 7. a clamp pulse, cl, is generated from mclk and vsmp by the timing control block. when cl is active the voltage on the WM8193 side of c in ,at rinp, is forced to the vrlc/vbias voltage (v vrlc ) by switch 1. when the cl pulse turns off, the voltage at rinp initially remains at v vrlc but any subsequent variation in sensor voltage (from reset to video level) will couple through c in to rinp. rlc is compatible with both cds and non-cds operating modes, as selected by switch 2. refer to the cds/non-cds processing section. WM8193 advanced information w ai rev 2.0 september 2002 12 timing control s/h 4-bit rlc dac cl + + - to offset dac rlc cds from control interface s/h v s r s from control interface mclk vsmp rlc/acyc input sampling block for red channel cds c in rinp vrlc/ vbias 2 1 externalvrlc vrlcext figure 7 reset level clamping and cds circuitry if auto-cycling is not required, rlc can be selected pixel-by-pixel by pin rlc/acyc. figure 8 illustrates control of rlc for a typical ccd waveform, with cl applied during the reset period. the input signal applied to the rlc pin is sampled on the positive edge of mclk that occurs during each vsmp pulse. the sampled level, high (or low) controls the presence (or absence) of the internal cl pulse on the next reset level. the position of cl can be adjusted by using control bits cdsref[1:0] (figure 9). if auto-cycling is required, pin rlc/acyc is no longer available for this function and control bit rlcint determines whether clamping is applied. figure 8 relationship of rlc pin, mclk and vsmp to internal clamp pulse, cl the vrlc/vbias pin can be driven internally by a 4-bit dac (rlcdac) by writing to control bits rlcv[3:0]. the rlcdac range and step size may be increased by writing to control bit rlcdacrng. alternatively, the vrlc/vbias pin can be driven externally by writing to control bit vrlcext to disable the rlcdac and then applying a d.c. voltage to the pin. mclk vsmp acyc/rlc or rlcint cl (cdsref = 01) input video 1x x 0x x 0 rgb rgb no rlc on this pixel rlc on this pixel programmable delay rgb advanced information WM8193 w ai rev 2.0 september 2002 13 cds/non-cds processing for ccd type input signals, the signal may be processed using cds, which will remove pixel-by-pixel common mode noise. for cds operation, the video level is processed with respect to the video reset level, regardless of whether rlc has been performed. to sample using cds, control bit cds must be set to 1 (default), this controls switch 2 (figure 7) and causes the signal reference to come from the video reset level. the time at which the reset level is sampled, by clock r s /cl, is adjustable by programming control bits cdsref[1:0], as shown in figure 9. mclk vsmp vs r s /cl(cdsref = 00) r s /cl(cdsref = 01) r s /cl(cdsref = 10) r s /cl(cdsref = 11) figure 9 reset sample and clamp timing for cis type sensor signals, non-cds processing is used. in this case, the video level is processed with respect to the voltage on pin vrlc/vbias, generated internally or externally as described above. the vrlc/vbias pin is sampled by r s at the same time as v s samples the video level in this mode. offset adjust and programmable gain the output from the cds block is a differential signal, which is added to the output of an 8-bit offset dac to compensate for offsets and then amplified by an 8-bit pga. the gain and offset for each channel are independently programmable by writing to control bits dac[7:0] and pga[7:0]. the gain characteristic of the WM8193 pga is shown in figure 10. figure 11 shows the maximum device input voltage that can be gained up to match the adc full-scale input range (3v). 0 1 2 3 4 5 6 7 8 0 64 128 192 256 gain register value (pga[7:0]) pga gain (v/v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 64 128 192 256 gain register value (pga[7:0]) peak input voltage to match adc full - scale input range figure 10 pga gain characteristic figure 11 peak input voltage to match adc full-scale range WM8193 advanced information w ai rev 2.0 september 2002 14 in colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order (red green blue red) by pulsing the acyc/rlc pin, or controlled via the fme, acycnrlc and intm[1:0] bits. refer to the line-by-line operation section for more details. adc input black level adjust the output from the pga should be offset to match the full-scale range of the adc (3v). for negative-going input video signals, a black level (zero differential) output from the pga should be offset to the top of the adc range by setting register bits pgafs[1:0]=10. for positive going input signal the black level should be offset to the bottom of the adc range by setting pgafs[1:0]=11. bipolar input video is accommodated by setting pgafs[1:0]=00 or pgafs[1:0]=01 (zero differential input voltage gives mid-range adc output). overall signal flow summary figure 12 represents the processing of the video signal through the WM8193. v reset v vrlc v 3 cds = 1 cds = 0 rlcext=1 260mv*(dac[7:0]-127.5)/127.5 analog - x + + see parametrics for dac voltages. op[15:0] d 1 digital adc block pga block offset dac block input sampling block d 2 cds, rlcext,rlcv[3:0], dac[7:0], pga[7:0], pgafs[1:0] and invop are set by programming internal control registers. cds=1 for cds, 0 for non-cds v in is rinp or ginp or binp v reset is v in sampled during reset clamp vrlc is voltage applied to vrlc pin v in x (65535/v fs ) +0 if pgafs[1:0]=11 +65535 if pgafs[1:0]=10 +32768 if pgafs[1:0]=0x pga gain a = 208/(283-pga[7:0]) output invert block d2 = d1 if invop = 0 d2 = 65535-d1 if invop = 1 offset dac rlc dac + v 2 v 1 rlcext=0 figure 12 overall signal flow the input sampling block produces an effective input voltage v 1 . for cds, this is the difference between the input video level v in and the input reset level v reset . for non-cds this is the difference between the input video level v in and the voltage on the vrlc/vbias pin, v vrlc , optionally set via the rlc dac. the offset dac block then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0v, producing v 2 . the pga block then amplifies the white level of the input signal to maximise the adc range, outputting voltage v 3 . the adc block then converts the analogue signal, v 3 , to a 16-bit unsigned digital output, d 1 . the digital output is then inverted, if required, through the output invert block to produce d 2. advanced information WM8193 w ai rev 2.0 september 2002 15 calculating output for any given input the following equations describe the processing of the video and reset level signals through the WM8193. input sampling block: input sampling and referencing if cds = 1, (cds operation) the previously sampled reset level, v reset , is subtracted from the input video. v 1 =v in -v reset ................................................................... eqn. 1 if cds = 0, (non-cds operation) the simultaneously sampled voltage on pin vrlc is subtracted instead. v 1 =v in -v vrlc .................................................................... eqn. 2 if rlcext = 1, v vrlc is an externally applied voltage on pin vrlc/vbias. if rlcext = 0, v vrlc is the output from the internal rlc dac. v vrlc =(v rlcstep ? rlcv[3:0]) + v rlcbot ................................. eqn. 3 v rlcstep is the step size of the rlc dac and v rlcbot is the minimum output of the rlc dac. offset dac block: offset (black-level) adjust the resultant signal v 1 is added to the offset dac output. v 2 = v 1 + {260mv ? (dac[7:0]-127.5) } / 127.5 ..................... eqn. 4 pga node: gain adjust the signal is then multiplied by the pga gain, v 3 = v 2 ? 208/(283- pga[7:0]) .............................................. eqn. 5 adc block: analogue-digital conversion the analogue signal is then converted to a 16-bit unsigned number, with input range configured by pgafs[1:0]. d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} + 32767 pgafs[1:0] = 00 or 01 ...... eqn. 6 d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} pgafs[1:0] = 11 ............... eqn. 7 d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} + 65535 pgafs[1:0] = 10 ............... eqn. 8 where the adc full-scale range, v fs =3v. output invert block: polarity adjust the polarity of the digital output may be inverted by control bit invop. d 2 [15:0] = d 1 [15:0] (invop = 0) ...................... eqn. 9 d 2 [15:0] = 65535 C d 1 [15:0] (invop = 1) ...................... eqn. 10 output formats the digital data output from the adc is available to the user in either 16-bit parallel or 8/4-bit wide multiplexed formats by setting control bits muxop[1:0]. latency of valid output data with respect to vsmp is programmable by writing to control bits del[1:0]. the latency for each mode is shown in the operating mode timing diagrams section. figure 13 shows the output data formats for modes 1 C 2 and 4 C 6. figure 14 shows the output data formats for mode 3. table 1 summarises the output data obtained for each format. WM8193 advanced information w ai rev 2.0 september 2002 16 mclk 4+4+4+4-bit output a ab d abc 16-bit parallel output 8+8-bit output mclk 4+4+4+4-bit output a ab 16-bit parallel output 8+8-bit output ab c d ab figure 13 output data formats (modes 1 ? ? ? ? 2, 4 ? ? ? ? 6) figure 14 output data formats (mode 3) output format muxop[1:0] output pins output 16-bit parallel 00 op[15:0] a = d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0 8+8-bit multiplexed 01 10 op[15:8] a = d15, d14, d13, d12, d11, d10, d9, d8 b = d7, d6, d5, d4, d3, d2, d1, d0 4+4+4+4-bit (nibble) 11 op[15:12] a = d15, d14, d13, d12 b = d11, d10, d9, d8 c = d7, d6, d5, d4 d = d3, d2, d1, d0 table 1 details of output data shown in figure 13 and figure 14. controlinterface the internal control registers are programmable via the serial or parallel digital control interface. the register contents can be read back via the parallel interface on pins op[15:8], or via the serial interface on pin op[15]/sdo. it is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. this ensures that all registers are set to their default values (as shown in table 5). serialinterface: register write figure 15 shows register writing in serial mode. three pins, sck, sdi and sen are used. a six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through sdi, msb first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also msb first. each bit is latched on the rising edge of sck. when the data has been shifted into the device, a pulse is applied to sen to transfer the data to the appropriate internal register. note all valid registers have address bit a4 equal to 0 in write mode. sck sen sdi a5 0 a3a2a1a0b7b6b5b4b3b2b1b0 address data word figure 15 serial interface register write using the serial interface, a software reset is carried out by writing to address 000100 with any value of data, (i.e. data word = xxxxxxxx). advanced information WM8193 w ai rev 2.0 september 2002 17 serialinterface: register read-back figure 16 shows register read-back in serial mode. read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output msb first on pin sdo (on the falling edge of sck). note that pin sdo is shared with an output pin, op[15], therefore oeb should always be held low when register read-back data is expected on this pin. the next word may be read in to sdi while the previous word is still being output on sdo. sck sen sdi a51a3a2a1a0xxxxxxxx address data word d7 d6 d5 d4 d3 d2 d1 d0 output data word sdo oeb figure 16 serial interface register read-back parallel interface: register write figure 17 shows register write in parallel mode. the parallel interface uses bits op[15:8] of the output bus and the stb, dna and rnw pins. pin rnw must be low during a write operation. the dna pin defines whether the data byte is address (low) or data (high). the 6-bit address (a5, 0, a3, a2, a1, a0) is input into op[13:8], lsb into op[8], (op[14] and op[15] are ignored) when dna is low, then the 8-bit data word is input into op[15:8], lsb into op[6], when dna is high. the data bus op[15:8] for both address and data is clocked in on the falling edge of stb. note all valid registers have address bit a4 equal to 0. stb dna rnw op[15:8] address data hi-z hi-z driven by afe driven externally normal output data driven by afe normal output data figure 17 parallel interface register write using the parallel interface, a software reset is carried out by writing 000100 to op[13:8] when rnw and dna are low. any value of data can be written for this address when dna changes to high (i.e. data = xxxxxxxx on op[15:8]). parallel interface: register read-back figure 18 shows register read-back in parallel mode. read-back is initiated by writing the 6-bit address (a5, 1, a3, a2, a1, a0) into op[13:8] by pulsing the stb pin low. note that a4 = 1 and pins rnw and dna are low. when rnw and dna are high and stb is strobed again, the contents (d7, d6, d5, d4, d3, d2, d1, d0) of the corresponding register (a5, 0, a3, a2, a1, a0) will be output on op[15:8], lsb on pin op[8]. until stb is pulsed low, the current contents of the adc (shown as normal output data) will be present on op[15:8]. note that the register data becomes available on the output data pins so oeb should be held low when read-back data is expected. WM8193 advanced information w ai rev 2.0 september 2002 18 stb dna rnw op[15:8] address hi-z driven by afe driven externally hi-z normal output data read data driven by afe normal output data figure 18 parallel interface register read-back timing requirements to use this device a master clock (mclk) of up to 12mhz and a per-pixel synchronisation clock (vsmp) of up to 6mhz are required. these clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. mclk to vsmp ratios and maximum sample rates for the various modes are shown in table 4. programmable vsmp detect circuit the vsmp input is used to determine the sampling point and frequency of the WM8193. under normal operation a pulse of 1 mclk period should be applied to vsmp at the desired sampling frequency (as shown in the operating mode timing diagrams) and the input sample will be taken on the first rising mclk edge after vsmp has gone low. however, in certain applications such a signal may not be readily available. the programmable vsmp detect circuit in the WM8193 allows the sampling point to be derived from any signal of the correct frequency, such as a ccd shift register clock, when applied to the vsmp pin. when enabled, by setting the vsmpdet control bit, the circuit detects either a rising or falling edge (determined by posnneg control bit) on the vsmp input pin and generates an internal vsmp pulse. this pulse can optionally be delayed by a number of mclk periods, specified by the vdel[2:0] bits. figure 19 shows the internal vsmp pulses that can be generated by this circuit for a typical clock input signal. the internal vsmp pulse is then applied to the timing control block in place of the normal vsmp pulse provided from the input pin. the sampling point then occurs on the first rising mclk edge after this internal vsmp pulse, as shown in the operating mode timing diagrams. advanced information WM8193 w ai rev 2.0 september 2002 19 mclk vsmp (vdel= 000) intvsmp posnneg = 1 (vdel= 001) intvsmp (vdel= 010) intvsmp (vdel= 011) intvsmp (vdel= 100) intvsmp (vdel= 101) intvsmp (vdel= 110) intvsmp (vdel= 111) intvsmp posnneg = 0 (vdel= 000) intvsmp (vdel= 001) intvsmp (vdel= 010) intvsmp (vdel= 011) intvsmp (vdel= 100) intvsmp (vdel= 101) intvsmp (vdel= 110) intvsmp (vdel= 111) intvsmp input pins v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s figure 19 internal vsmp pulses generated by programmable vsmp detect circuit references the adc reference voltages are derived from an internal bandgap reference, and buffered to pins vrt and vrb, where they must be decoupled to ground. pin vrx is driven by a similar buffer, and also requires decoupling. the output buffer from the rlcdac also requires decoupling at pin vrlc/vbias. power supply the WM8193 can run from a 5v single supply or from split 5v (core) and 3.3v (digital interface) supplies. WM8193 advanced information w ai rev 2.0 september 2002 20 power management power management for the device is performed via the control interface. the device can be powered on or off completely by setting the en bit and selpd bit low. alternatively, when control bit selpd is high, only blocks selected by further control bits (seldis[3:0]) are powered down. this allows the user to optimise power dissipation in certain modes, or to define an intermediate standby mode to allow a quicker recovery into a fully active state. in line-by-line operation, the green and blue channel pgas are automatically powered down. all the internal registers maintain their previously programmed value in power down modes and the control interface inputs remain active. table 2 summarises the power down control bit functions. en seldpd 00 device completely powers down. 10 device completely powers up. x1 blocks with respective seldis[3:0] bit high are disabled. table 2 power down control line-by-line operation certain linear sensors (e.g. contact image sensors) give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. in order to accommodate this type of signal the WM8193 can be set into monochrome mode, with the input channel switched by writing to control bits chan[1:0] between every line. alternatively, the WM8193 can be placed into colour line-by-line mode by setting the linebyline control bit. when this bit is set the green and blue processing channels are powered down and the device is forced internally to only operate in mono mode (because only one colour is sampled at a time) through the red channel. figure 20 shows the signal path when operating in colour line-by-line mode. rinp sen/stb v smp mclk v rlc/vbias sdi/dna sck/rnw rlc/acyc rlc binp ginp input mux offset mux rlc r g b r g b pga i/p signal polarity adjust 8 rlc dac + configurable serial/ parallel control interface op[15:0] + 16- bit adc data i/o port 8 offset dac pga mux timing control clv s r s 4 cds rlc nreset figure 20 signal path when in line-by-line mode in this mode the input multiplexer and (optionally) the pga/offset register multiplexers can be auto- cycled by the application of pulses to the rlc/acyc input pin by setting the acycnrlc register bit. see figure 4 for detailed timing information. the multiplexers change on the first mclk rising edge after rlc/acyc is taken high. a write to the auto-cycle reset register causes these multiplexers to be reset; selecting the rinp pin and the red offset/gain registers. alternatively, all three multiplexers can be controlled via the serial interface by writing to register bits intm[1:0] to select the desired colour. it is also possible for the input multiplexer to be controlled separately from the pga and offset multiplexers. table 4 describes all the multiplexer selection modes that are possible. advanced information WM8193 w ai rev 2.0 september 2002 21 fme acycnrlc name description 00 internal, no force mux input mux, offset and gain registers determined by internal register bits intm1, intm0. 01 auto-cycling, no force mux input mux, offset and gain registers auto-cycled, rinp ginp binp rinp on rlc/acyc pulse. 10 internal, force mux input mux selected from internal register bits fm1, fm0; offset and gain registers selected from internal register bits intm1, intm0. 11 auto-cycling, force mux input mux selected from internal register bits fm1, fm0; offset and gain registers auto-cycled, red green blue red on rlc/acyc pulse. table 3 colour selection description in line-by-line mode WM8193 advanced information w ai rev 2.0 september 2002 22 operating modes table 4 summarises the most commonly used modes, the clock waveforms required and the register contents required for cds and non-cds operation. mode description cds available max sample rate sensor interface description timing require- ments register contents with cds register contents without cds 1 colour pixel-by-pixel yes 2msps x 3 chans the 3 input channels are sampled in parallel. the signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the adc, giving an output data rate of 6msps max. mclk max = 12mhz mclk: vsmp ratio is 6:1 setreg1: 03(hex) setreg1: 01(hex) 2 monochrome/ colour line-by-line yes 2msps as mode 1 except: only one input channel at a time is continuously sampled. mclk max = 12mhz mclk: vsmp ratio is 6:1 setreg1: 07(hex) setreg1: 05(hex) 3 fast monochrome/ colour line-by-line yes 4msps identical to mode 2 mclk max = 12mhz mclk: vsmp ratio is 3:1 identical to mode 2 plus setreg3: bits 5:4 must be set to 0(hex) identical to mode 2 4 maximum speed monochrome/ colour line-by-line no 6msps identical to mode 2 mclk max = 12mhz mclk: vsmp ratio is 2:1 cds not possible setreg1: 45(hex) 5 slow colour pixel-by-pixel yes 1.5msps x 3 chans identical to mode 1 mclk max = 12mhz mclk: vsmp ratio is 2n:1, n 4 identical to mode 1 identical to mode 1 6 slow monochrome/ colour line-by-line yes 1.5msps identical to mode 2 mclk max = 12mhz mclk: vsmp ratio is 2n:1, n 4 identical to mode 2 identical to mode 2 table 4 WM8193 operating modes notes: 1. in monochrome mode, setup register 3 bits 7:6 determine which input is to be sampled. 2. for colour line-by-line, set control bit linebyline. for input selection, refer to table 4 colour selection description in line-by-line mode. advanced information WM8193 w ai rev 2.0 september 2002 23 operating mode timing diagrams the following diagrams show 16-bit parallel format output and mclk, vsmp and input video requirements for operation of the most commonly used modes as shown in table 4. the diagrams are identical for both cds and non-cds operation. outputs from rinp, ginp and binp are shown as r, g and b respectively. x denotes invalid data. mclk vsmp input video op[15:0] (del= 00) op[15:0] (del= 01) op[15:0] (del= 10) op[15:0] (del= 11) 16.5 mclk periods g b r g b r g r b r b g r r g b r g b r b g b g r b r b r g b r g b g r g r b g b r g b r g b r g r b r b g r g b g g b figure 21 mode 1 operation 16.5 mclk periods mclk vsmp input video op[15:0] (del= 00) op[15:0] (del= 01) op[15:0] (del= 10) op[15:0] (del= 11) x x r x x r x r x r x x r r x x r x x r x x x x r x x r x x r x x x r x r x x x x r x x r x r x r x x r figure 22 mode 2 operation mclk vsmp op[15:0] (del= 00) input video op[15:0] (del= 01) op[15:0] (del= 10) op[15:0] (del= 11) 23.5 mclk periods r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r figure 23 mode 3 operation WM8193 advanced information w ai rev 2.0 september 2002 24 mclk vsmp input video op[15:0] (del= 00) op[15:0] (del= 01) op[15:0] (del= 10) op[15:0] (del= 11) 16.5 mclk periods r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r figure 24 mode 4 operation mclk vsmp input video op[15:0] (del= 00) op[15:0] (del= 01) op[15:0] (del= 10) op[15:0] (del= 11) 16.5 mclk periods g b r b g r g b r x x x r g x g r x r g x b b b x r b r x b x r b g g g b x g x b g b x g r r r b x g b r x r g b x r g figure 25 mode 5 operation (mclk:vsmp ratio = 8:1) mclk vsmp input video op[15:0] (del= 00) op[15:0] (del= 01) op[15:0] (del= 10) op[15:0] (del= 11) 16.5 mclk periods r r r x x x x x x x x x x x x x r x x r x x r x x x x x x r x x r x x r x x x r x x r x x r x x r x x x figure 26 mode 6 operation (mclk:vsmp ratio = 8:1) advanced information WM8193 w ai rev 2.0 september 2002 25 device configuration register map the following table describes the location of each control bit used to determine the operation of the WM8193. the register map is programmed by writing the required codes to the appropriate addresses via the serial or parallel interface. bit address WM8193 advanced information w ai rev 2.0 september 2002 26 register map description the following table describes the function of each of the control bits shown in table 5. register bit no bit name(s) default description 0en 1 when selpd = 1 this bit has no effect. when selpd = 0 this bit controls the global power down: 0 = complete power down, 1 = fully active. 1cds 1 select correlated double sampling mode: 0 = single ended mode, 1 = cds mode. 2mono 0 mono/colour select: 0 = colour, 1 = monochrome operation. 3 selpd 0 selective power down: 0 = no individual control, 1 = individual blocks can be disabled (controlled by seldis[3:0]). offsets pga output to optimise the adc range for different polarity sensor output signals. zero differential pga input signal gives: 5:4 pgafs[1:0] 00 00 = zero output (use for bipolar video) 01 = zero output 10 = full-scale positive output (use for negative going video) 11 = full-scale negative output (use for positive going video) setup register 1 6mode4 0 required when operating in mode4: 0 = other modes, 1 = mode4. determines the output data format. 1:0 muxop[1:0] 00 00 = 16-bit parallel 01 = 8-bit multiplexed (8+8 bits) 10 = 8-bit multiplexed mode (8+8 bits) 11 = 4-bit multiplexed mode (4+4+4+4 bits) 2invop 0 digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative going video gives positive going output data. 3vrlcext 0 when set powers down the rlcdac, changing its output to hi-z, allowing vrlc/vbias to be externally driven. 5 rlcdacrng 1 sets the output range of the rlcdac. 0 = rlcdac ranges from 0 to avdd (approximately), 1 = rlcdac ranges from 0 to vrt (approximately). sets the output latency in adc clock periods. 1 adc clock period = 2 mclk periods except in mode 3 where 1 adc clock period = 3 mclk periods. setup register 2 7:6 del[1:0] 00 00 = minimum latency 01 = delay by one adc clock period 10 = delay by two adc clock periods 11 = delay by three adc clock periods 3:0 rlcv[3:0] 1111 controls rlcdac driving vrlc/vbias pin to define single ended signal reference voltage or reset level clamp voltage. see electrical characteristics section for ranges. cds mode reset timing adjust. 5:4 cdsref[1:0] 01 00 = advance 1 mclk period 01 = normal 10 = retard 1 mclk period 11 = retard 2 mclk periods monochrome mode channel select. setup register 3 7:6 chan[1:0] 00 00 = red channel select 01 = green channel select 10 = blue channel select 11 = reserved software reset any write to software reset causes all cells to be reset. it is recommended that a software reset be performed after a power-up before any other register writes. auto-cycle reset any write to auto-cycle reset causes the auto-cycle counter to reset to rinp. this function is only required when lin ebyline = 1. advanced information WM8193 w ai rev 2.0 september 2002 27 register bit no bit name(s) default description 0 linebyline 0 selects line by line operation 0 = normal operation, 1 = line by line operation. when line by line operation is selected mono is forced to 1 and chan[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. green and blue pgas are also disabled to save power. 1 acycnrlc 0 when linebyline = 0 this bit has no effect. when linebyline = 1 this bit determines the function of the rlc/acyc input pin and the input multiplexer and offset/gain register controls. 0 = rlc/acyc pin enabled for reset level clamp. internal selection of input and gain/offset multiplexers, 1 = auto-cycling enabled by pulsing the rlc/acyc input pin. see table 4, colour selection description in line-by-line mode for colour selection mode details. when auto-cycling is enabled, the rlc/acyc pin cannot be used for reset level clamping. the rlcint bit may be used instead. 2fme 0 when linebyline = 0 this bit has no effect. when linebyline = 1 this bit controls the input force mux mode: 0 = no force mux, 1 = force mux mode. forces the input mux to be selected by fm[1:0] separately from gain and offset multiplexers. see table 4 for details. 3rlcint 0 when linebyline = 1 and acycnrlc = 1 this bit is used to determine whether reset level clamping is used. 0 = rlc disabled, 1 = rlc enabled. 5:4 intm[1:0] 00 colour selection bits used in internal modes. 00 = red, 01 = green, 10 = blue and 11 = reserved. see table 4 for details. setup register 4 7:6 fm[1:0] 00 colour selection bits used in input force mux modes. 00 = rinp, 01 = ginp, 10 = binp and 11 = reserved. see table 4 for details. 0 vsmpdet 0 0 = normal operation, signal on vsmp input pin is applied directly to timing control block. 1 = programmable vsmp detect circuit is enabled. an internal synchronisation pulse is generated from signal applied to vsmp input pin and is applied to timing control block. 3:1 vdel[2:0] 000 when vsmpdet = 0 these bits have no effect. when vsmpdet = 1 these bits set a programmable delay from the detected edge of the signal applied to the vsmp pin. the internally generated pulse is delayed by vdel mclk periods from the detected edge. see figure 19, internal vsmp pulses generated for details. setup register 5 4 posnneg 0 when vsmpdet = 0 this bit has no effect. when vsmpdet = 1 this bit controls whether positive or negative edges are detected: 0 = negative edge on vsmp pin is detected and used to generate internal timing pulse. 1 = positive edge on vsmp pin is detected and used to generate internal timing pulse. see figure 19 for further details. setup register 6 3:0 seldis[3:0] 0000 selective power disable register - activated when selpd = 1. each bit disables respective cell when 1, enabled when 0. seldis[0] = red cds, pga seldis[1] = green cds, pga seldis[2] = blue cds, pga seldis[3] = adc WM8193 advanced information w ai rev 2.0 september 2002 28 register bit no bit name(s) default description offset dac (red) 7:0 dac[7:0] 0 red channel offset dac value. offset dac (green) 7:0 dac[7:0] 0 green channel offset dac value offset dac (blue) 7:0 dac[7:0] 0 blue channel offset dac value offset dac (rgb) 7:0 dac[7:0] 0 a write to this register location causes the red, green and blue offset dac registers to be overwritten by the new value pga gain (red) 7:0 pga[7:0] 0 determines the gain of the red channel pga according to the equation: red channel pga gain = 208/(283-pga[7:0]) pga gain (green) 7:0 pga[7:0] 0 determines the gain of the green channel pga according to the equation: green channel pga gain = 208/(283-pga[7:0]) pga gain (blue) 7:0 pga[7:0] 0 determines the gain of the blue channel pga according to the equation: blue channel pga gain = 208/(283-pga[7:0]) pga gain (rgb) 7:0 pga[7:0] 0 a write to this register location causes the red, green and blue pga gain registers to be overwritten by the new value table 6 register control bits advanced information WM8193 w ai rev 2.0 september 2002 29 recommended externalcomponents 10 24 8 6 4 17 15 16 12 14 13 dvdd1 dvdd2 agnd1 rinp ginp binp mclk vsmp rlc/acyc sen/stb sdi/dna sck/rnw 18 2 48 1 47 31 29 28 27 26 23 22 21 op[2] op[3] op[4] op[5] op[6] op[7] op[8] op[9] vrlc/vbias vrx vrt vrb c 2 c 1 c 7 c 9 c 5 c 6 c 8 c 10 video inputs timing signals interface controls output data bus agnd agnd agnd 3 dgnd1 agnd2 5 WM8193 25 dgnd2 30 dgnd3 36 dgnd4 40 dgnd5 agnd3 7 agnd4 9 agnd5 45 agnd6 46 32 op[10] 33 op[11] 34 op[12] 37 op[13] 38 op[14] 39 op[15]/sdo avdd1 avdd 43 c 4 agnd 35 dvdd3 c 3 dgnd dvdd1 avdd2 44 42 nreset 11 oeb dvdd2, 3 c 11 dvdd1 + c 12 dvdd2, 3 + c 13 avdd1, 2 + agnd op[0] 19 op[1] 20 c1-10 should be fitted as close to WM8193 as possible. 1. 2. agnd1-6 and dgnd1-5 should be connected as close to WM8193 as possible. notes: 3. dvdd1-3 should be connected as close to WM8193 as possible. figure 27 external components diagram WM8193 advanced information w ai rev 2.0 september 2002 30 component reference suggested value description c1 100nf de-coupling for dvdd1. c2 100nf de-coupling for dvdd2. c3 100nf de-coupling for dvdd3. c4 100nf de-coupling for avdd1 and avdd2. c5 10nf high frequency de-coupling between vrt and vrb. c6 1 f low frequency de-coupling between vrt and vrb (non-polarised). c7 100nf de-coupling for vrb. c8 100nf de-coupling for vrx. c9 100nf de-coupling for vrt. c10 100nf de-coupling for vrlc. c11 1 f reservoir capacitor for dvdd1. c12 1 f reservoir capacitor for dvdd2 and dvdd3. c13 1 f reservoir capacitor for avdd1 and avdd2. table 7 external components descriptions advanced information WM8193 w ai rev 2.0 september 2002 31 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 ms-026, variation = abc. refer to this specification for further details. dm004.c ft:48pintqfp (7x7x1.0mm) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.05 ----- 0.15 a 2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 ----- 0.20 d 9.00 bsc d 1 7.00 bsc e 9.00 bsc e 1 7.00 bsc e 0.50 bsc l 0.45 0.60 0.75 0 o 3.5 o 7 o tolerances of form and position ccc 0.08 ref: jedec.95, ms-026 25 36 e b 12 1 d1 d e1 e 13 24 37 48 a a2 a1 seating plane ccc c -c- c l WM8193 advanced information w ai rev 2.0 september 2002 32 important notice wolfson microelectronics ltd (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wmterms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wmwarrants performance of its products to the specifications applicable at the time of sale in accordance with wms standard warranty. testing and other quality control techniques are utilised to the extent wmdeems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wmassumes no liability for applications assistance or customer product design. wmdoes not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wmcovering or relating to any combination, machine, or process in which such products or services might be or are used. wms publication of information regarding any third partys products or services does not constitute wms approval, license, warranty or endorsement thereof. reproduction of information from the wmweb site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wmproduct or service, is an unfair and deceptive business practice, and wmis not responsible nor liable for any such use. resale of wms products or services with statements different from or beyond the parameters stated by wmfor that product or service voids all express and any implied warranties for the associated wmproduct or service, is an unfair and deceptive business practice, and wmis not responsible nor liable for any such use. address: wolfson microelectronics ltd 20 bernard terrace edinburgh eh8 9nx united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com |
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